Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for store dependence prediction.
Description of the Related Art
When a load-from-memory operation (referred to as a “load micro-operation” or “load uop” in certain processor nomenclatures) is dispatched for execution in a pipelined processor, it checks against older, in-flight, store-to-memory operations (“store uops”) in the store buffer. This is necessary because there can be an older store operation with a matching memory address that hasn't written its data into the memory hierarchy yet. If there is such a matching store, the load uop either forwards from the youngest older matching store or waits until the store is completed (depending on the “forwardability” of the data). This address checking process against older stores for possible dependency is commonly referred to as Memory Disambiguation.
If a store's address has not been calculated yet by the time of load dispatch, the load uop would have to conservatively consider the store's address as potentially matching and wait until the store address is resolved. To reduce the performance impact of those store address-induced blocks, certain processors employ a load-based dependence prediction mechanism. The load-based predictor monitors load execution and records whether there was a matching store. If not, later loads are allowed to speculatively treat those stores whose address hasn't been resolved yet as non-match. Many times this leads to faster completion of loads as they do not block on those stores which do not yet have a valid address. Stores need to check against completed younger loads to verify if the prediction was indeed correct.